Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure.
The logic blocks and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Some FPGAs also include additional logic blocks with special purposes in the configurable array. For example, the Xilinx Virtex-II Pro™ FPGA includes blocks of Random Access Memory (RAM), blocks implementing multiplier functions, and embedded processor blocks. (The Xilinx Virtex-II Pro FPGA is described in detail in pages 19–71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
FPGAs are increasing in size with each product generation. At the same time, the minimum feature size (e.g., gate length, metal width, and so forth) is decreasing. Each of these trends increases the susceptibility of the FPGA to manufacturing defects. Therefore, it is desirable to provide structures and methods that reduce the susceptibility of FPGA circuits to manufacturing defects. It is particularly desirable to reduce the susceptibility of repetitive circuits to manufacturing defects. For example, if a logic block that is repeated many times is rendered less susceptible, the gain in product yield is larger than the gain resulting from a similar improvement to a circuit that is included only once. Further, it is particularly desirable to reduce the susceptibility of circuits that can be unusually sensitive to manufacturing defects, such as memory cells in a RAM array that typically comprise minimum-sized transistors designed to consume the smallest possible area.
A known method of reducing susceptibility to manufacturing defects in a PLD RAM array is to include a redundant column of memory cells in the RAM array. For example, such a method is described by Cliff et al. in U.S. Pat. No. 5,498,975 entitled “Implementation of Redundancy on a Programmable Logic Device”, which is hereby incorporated herein by reference. When this type of PLD RAM array is used, each column of memory cells is tested during the PLD testing process. If a defect is detected in any column in the array, fuses are blown to effectively bypass the column of RAM cells. The device then functions with a column offset in the array, but in a manner transparent to the PLD user. In some cases, non-volatile memory cells (e.g., EEPROM or flash cells) are used to control the column selection instead of fuses.
However, this type of device has its disadvantages. For example, the fuses or non-volatile memory cells must be manufactured as part of the PLD, which adds to the manufacturing complexity and cost. An additional disadvantage of fuse-based methods is that the testing and repair are typically performed “at the factory” (prior to shipping to the user), and any column offset is made permanent at that time. If a defect develops (i.e., one or more of the RAM columns ceases to operate correctly) after the column offset procedure is performed and the device is already in place within the target system, it is then too late to repair the defect. Even if non-volatile memory cells are used, reprogramming of the non-volatile memory cells typically involves the use of a separate piece of programming hardware that might be unavailable within the user's system.
Therefore, it is desirable to provide methods and structures for self-test and self-repair of PLD RAM arrays.